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| PMV117EN TrenchMOSTM enhanced logic level FET Rev. 02 -- 7 April 2005 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOSTM technology. 1.2 Features s Logic level threshold s Subminiature surface-mounted package s Very fast switching 1.3 Applications s Battery management s High-speed switch s Low power DC-to-DC converter 1.4 Quick reference data s VDS 30 V s RDSon 117 m (VGS = 10 V) s ID 2.5 A s Ptot 0.83 W 2. Pinning information Table 1: Pin 1 2 3 Pinning Description gate (G) source (S) drain (D) 1 2 3 D Simplified outline Symbol G SOT23 mbb076 S Philips Semiconductors PMV117EN TrenchMOSTM enhanced logic level FET 3. Ordering information Table 2: Ordering information Package Name PMV117EN TO-236AB Description plastic surface mounted package; 3 leads Version SOT23 Type number 4. Limiting values Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM drain-source voltage (DC) drain-gate voltage (DC) gate-source voltage (DC) drain current (DC) peak drain current total power dissipation storage temperature junction temperature source (diode forward) current (DC) Tsp = 25 C peak source (diode forward) current Tsp = 25 C; pulsed; tp 10 s Tsp = 25 C; VGS = 10 V; Figure 2 and 3 Tsp = 100 C; VGS = 10 V; Figure 2 Tsp = 25 C; pulsed; tp 10 s; Figure 3 Tsp = 25 C; Figure 1 Conditions 25 C Tj 150 C 25 C Tj 150 C; RGS = 20 k Min -65 -65 Max 30 30 20 2.5 1.6 10 0.83 +150 +150 0.8 3.3 Unit V V V A A A W C C A A Source-drain diode 9397 750 14709 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 02 -- 7 April 2005 2 of 12 Philips Semiconductors PMV117EN TrenchMOSTM enhanced logic level FET 120 Pder (%) 80 03aa17 120 Ider (%) 80 03aa25 40 40 0 0 50 100 150 Tsp (C) 200 0 0 50 100 150 Tsp (C) 200 P tot P der = ------------------------ x 100 % P tot ( 25 C ) VGS 10 V ID I der = -------------------- x 100 % I D ( 25 C ) Fig 1. Normalized total power dissipation as a function of solder point temperature 102 ID (A) 10 Limit RDSon = VDS / ID Fig 2. Normalized continuous drain current as a function of solder point temperature 03ak56 tp = 10 s 100 s 1 DC 10-1 1 ms 10 ms 100 ms 10-2 10-1 1 10 VDS (V) 102 Tsp = 25 C; IDM is single pulse Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage 9397 750 14709 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 02 -- 7 April 2005 3 of 12 Philips Semiconductors PMV117EN TrenchMOSTM enhanced logic level FET 5. Thermal characteristics Table 4: Rth(j-sp) Thermal characteristics Conditions Figure 4 Min Typ Max 100 Unit K/W thermal resistance from junction to solder point Symbol Parameter 103 Zth(j-sp) (K/W) 102 = 0.5 0.2 10 0.1 0.05 0.02 single pulse 1 10-4 P 03ak55 = tp T tp T t 10-3 10-2 10-1 1 tp (s) 10 Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration 9397 750 14709 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 02 -- 7 April 2005 4 of 12 Philips Semiconductors PMV117EN TrenchMOSTM enhanced logic level FET 6. Characteristics Table 5: Characteristics Tj = 25 C unless otherwise specified. Symbol Parameter Static characteristics V(BR)DSS drain-source breakdown voltage ID = 10 A; VGS = 0 V Tj = 25 C Tj = -55 C VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Figure 9 and 10 Tj = 25 C Tj = 150 C Tj = -55 C IDSS drain-source leakage current VDS = 24 V; VGS = 0 V Tj = 25 C Tj = 150 C IGSS RDSon gate-source leakage current drain-source on-state resistance VGS = 20 V; VDS = 0 V VGS = 10 V; ID = 500 mA; Figure 6 and 8 Tj = 25 C VGS = 4.5 V; ID = 500 mA; Figure 6 and 8 Tj = 25 C Tj = 150 C Dynamic characteristics Qg(tot) Qgs Qgd Ciss Coss Crss td(on) tr td(off) tf VSD trr total gate charge gate-source charge gate-drain (Miller) charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time source-drain (diode forward) voltage reverse recovery time IS = 0.83 A; VGS = 0 V; Figure 12 IS = 1 A; dIS/dt = -100 A/s; VGS = 0 V; VDS = 25 V VDD = 15 V; RL = 15 ; VGS = 10 V VGS = 0 V; VDS = 10 V; f = 1 MHz; Figure 13 ID = 0.5 A; VDD = 15 V; VGS = 10 V; Figure 11 4.6 0.6 1.35 147 65 41 4 7.5 18 13 0.7 69 1.2 nC nC nC pF pF pF ns ns ns ns V ns 117 188 190 300 m m 74 117 m 0.01 10 0.5 10 100 A A nA 1.5 1.1 2 2.7 V V V 30 27 37 V V Conditions Min Typ Max Unit Source-drain diode 9397 750 14709 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 02 -- 7 April 2005 5 of 12 Philips Semiconductors PMV117EN TrenchMOSTM enhanced logic level FET 3 ID (A) 03ak57 10 6 4.5 3.8 3.6 3.4 400 RDSon (m) 03ak58 Tj = 25 C VGS (V) = 3 3.2 3.4 3.2 300 2 3 200 3.8 2.8 2.6 VGS (V) = 2.4 100 3.6 1 4.5 6 10 0 0 0.2 0.4 0.6 0.8 VDS (V) 1 0 0 1 2 ID (A) 3 Tj = 25 C Tj = 25 C Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values 3 VDS > ID x RDSon ID (A) 2 03ak59 Fig 6. Drain-source on-state resistance as a function of drain current; typical values 2 a 1.5 03ad57 1 1 Tj = 150 C 25 C 0.5 0 0 1 2 3 VGS (V) 4 0 -60 0 60 120 Tj (C) 180 Tj = 25 C and 150 C; VDS > ID x RDSon R DSon a = ----------------------------R DSon ( 25 C ) Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature Fig 7. Transfer characteristics: drain current as a function of gate-source voltage; typical values 9397 750 14709 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 02 -- 7 April 2005 6 of 12 Philips Semiconductors PMV117EN TrenchMOSTM enhanced logic level FET 2.5 VGS(th) (V) 2 typ 03ak63 10-1 ID (A) 10-2 03ak64 min 1.5 10-3 min typ 1 10-4 0.5 10-5 0 -60 10-6 0 60 120 Tj (C) 180 0 0.8 1.6 2.4 VGS (V) 3.2 ID = 1 mA; VDS = VGS Tj = 25 C; VDS = 5 V Fig 9. Gate-source threshold voltage as a function of junction temperature 10 VGS (V) 8 ID = 0.5 A Tj = 25 C VDD = 15 V Fig 10. Sub-threshold drain current as a function of gate-source voltage 03ak62 6 4 2 0 0 2 4 QG (nC) 6 ID = 0.5 A; VDD = 15 V Fig 11. Gate-source voltage as a function of gate charge; typical values 9397 750 14709 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 02 -- 7 April 2005 7 of 12 Philips Semiconductors PMV117EN TrenchMOSTM enhanced logic level FET 3 VGS = 0 V IS (A) 03ak60 103 03ak61 C (pF) 2 Ciss 102 Coss 1 Tj = 150 C 25 C Crss 0 0 0.3 0.6 0.9 VSD (V) 1.2 10 10-1 1 10 VDS (V) 102 Tj = 25 C and 150 C; VGS = 0 V VGS = 0 V; f = 1 MHz Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values Fig 13. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values 9397 750 14709 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 02 -- 7 April 2005 8 of 12 Philips Semiconductors PMV117EN TrenchMOSTM enhanced logic level FET 7. Package outline Plastic surface mounted package; 3 leads SOT23 D B E A X HE vMA 3 Q A A1 1 e1 e bp 2 wMB detail X Lp c 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 max. 0.1 bp 0.48 0.38 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 e 1.9 e1 0.95 HE 2.5 2.1 Lp 0.45 0.15 Q 0.55 0.45 v 0.2 w 0.1 OUTLINE VERSION SOT23 REFERENCES IEC JEDEC TO-236AB JEITA EUROPEAN PROJECTION ISSUE DATE 99-09-13 04-11-04 Fig 14. Package outline SOT23 9397 750 14709 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 02 -- 7 April 2005 9 of 12 Philips Semiconductors PMV117EN TrenchMOSTM enhanced logic level FET 8. Revision history Table 6: Revision history Release date 20050407 Data sheet status Product data sheet Change notice Doc. number 9397 750 14709 Supersedes PMV117EN-01 Document ID PMV117EN_2 Modifications: * * * The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. Table 5 "Characteristics"; correction to VGS(th) data Table 2 "Ordering information": added Product data 9397 750 11095 - PMV117EN-01 20030226 9397 750 14709 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 02 -- 7 April 2005 10 of 12 Philips Semiconductors PMV117EN TrenchMOSTM enhanced logic level FET 9. Data sheet status Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). III Product data Production [1] [2] [3] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 10. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 12. Trademarks TrenchMOS -- is a trademark of Koninklijke Philips Electronics N.V. 11. Disclaimers Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 13. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com 9397 750 14709 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 02 -- 7 April 2005 11 of 12 Philips Semiconductors PMV117EN TrenchMOSTM enhanced logic level FET 14. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 10 11 12 13 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information . . . . . . . . . . . . . . . . . . . . 11 (c) Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 7 April 2005 Document number: 9397 750 14709 Published in The Netherlands |
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